The invention herein discloses algorithms for applying Lithographic Proximity Correction (LPC) to very large scale integrated (VLSI) circuit design databases to compensate for 1-dimensional (1-D) photolithographic errors.
Lithographic proximity correction (LPC) is used in very large scale integrated circuits to correct for printing errors such as one-dimensional lithographic errors. In integrated circuits having printed shapes with sizes that approach the wavelength of exposure, one-dimensional lithographic printing errors may occur because of electromagnetic diffraction from parallel edges of a mask feature during the lithographic printing process. For example, densely placed parallel transistor gates can be affected by this diffraction phenomenon differently from isolated transistor gates. Additionally, reticle, photoresist diffusion, and etch effects can cause 1-D lithographic printing errors. LPC is used to correct for these optical and non-optical undesirable printing errors, by adding or subtracting other features or shapes to or from the original design shape. The other features are used to modify the original design in order to compensate for certain undesirable effects that may take place during printing.
FIG. 1 and FIG. 2 together are used to illustrate a one-dimensional proximity effect. FIG. 1 illustrates original shapes 10, 11 and 12. Shapes 10, 11 and 12 are original design shapes positioned adjacent to each other, and separated by a certain minimum spacing. FIG. 2 illustrates original shapes 10, 11 and 12 as they would appear 10', 11' and 12' after printing due to one-dimensional lithographic proximity effects. The portion of shape 11' which is not located near another shape tends to be larger than that portion of 11' which is positioned between shapes 10' and 12'. These types of one-dimensional proximity effects adversely affect the effective gate length in an integrated circuit where shapes 10', 11' and 12' are formed from a polysilicon layer on top of a semiconductor substrate 13, and are used to create transistor gates.
FIG. 3 and FIG. 4 together illustrate features which may be used to correct or compensate for the one-dimensional proximity effects illustrated by FIG. 1 and FIG. 2. FIG. 3 illustrates the positioning of edge biases 14, 15, 16 and 17 with the edges of original shapes 10, 11 and 12 to increase the effective width of original shapes 10, 11 and 12 beyond the original designed dimensions in order to print at their original design dimensions. So, unlike the shape 11' illustrated in FIG. 2, shape 11 illustrated in FIG. 3 will have a uniform width throughout its length. FIG. 4. illustrates assist features for correcting one-dimensional proximity effects. In FIG. 4, a uniform width of shape 11 is provided by using subresolution assist features 19 and 20 to simulate an area of high density shapes without actually printing additional shapes. Assist features 19 and 20 are intentionally too narrow to print because they are substantially narrower than the resolution limit of a lithographic process.
Edge biasing features are generally used in areas where there are many closely spaced shapes. On the other hand, assist features are generally used in isolated areas.